| Name of the faculty : Annu Mahor | ||||
| Discipline : B-Tech | ||||
| Semester : VII Sem | ||||
| Subject : ADVANCED COMPUTER ARCHITECTURE | ||||
| Lesson plan duration : From July 2018 to Oct 2018 | ||||
| Work load lecture per week (in hours) : 4 Lectures | ||||
| Week | Theory | Practical | ||
| Lecture Day | Topic(including assignement/ test) | Practical Day | Topic | |
| 1 | 1 | Architecture And Machines: Some definition and terms | *** | *** |
| 2 | interpretation and microprogramming | *** | *** | |
| 3 | The instruction set | *** | *** | |
| 4 | Basic data types | |||
| 2 | 5 | Instructions, Addressing and Memory. | *** | *** |
| 6 | Virtual to real mapping. | *** | *** | |
| 7 | Basic Instruction Timing. | *** | *** | |
| 8 | Time, Area And Instruction Sets: Time, | *** | *** | |
| 3 | 9 | cost-area, technology state of the Art, | *** | *** |
| 10 | data flow guided testing. | *** | *** | |
| 11 | The Economics of a processor project: a study | *** | *** | |
| 12 | Instruction sets, Professor Evaluation Matrix | |||
| 4 | 13 | Test/Assignment | *** | *** |
| 14 | Cache Memory Notion: Basic Notion | *** | *** | |
| 15 | Cache Organization, Cache Data | *** | *** | |
| 16 | adjusting the data for cache organization | *** | *** | |
| 5 | 17 | policies | *** | *** |
| 18 | strategies for line replacement at miss time | *** | *** | |
| 19 | Cache Environment, other types of Cache | *** | *** | |
| 20 | chip caches, Two level Caches | |||
| 6 | 21 | write assembly Cache | *** | *** |
| 22 | Cache references per instruction | |||
| 23 | technology dependent Cache considerations | *** | *** | |
| 24 | virtual to real translation | *** | *** | |
| 7 | 25 | overlapping the Tcycle in V-R Translation | ||
| 26 | studies. Design summary | *** | *** | |
| 27 | Test/Assignment | *** | *** | |
| 28 | Memory System Design: The physical memory | |||
| 8 | 29 | models of simple processor memory interaction | *** | *** |
| 30 | processor memory modeling using queuing theory, | *** | *** | |
| 31 | open, closed and mixed-queue models, | *** | *** | |
| 32 | waiting time, performance | |||
| 9 | 33 | buffer size, review | *** | *** |
| 34 | selection of queuing models, | |||
| 35 | processors with cache. | *** | *** | |
| 36 | revision | |||
| 10 | 37 | Test/Assignment | *** | *** |
| 38 | Concurrent Processors: Vector Processors | *** | *** | |
| 39 | Vector Memory, Multiple Issue Machines | *** | *** | |
| 40 | Comparing vector and Multiple Issue processors | |||
| 11 | 41 | Shared Memory Multiprocessors: Basic issues | *** | *** |
| 42 | partitioning, synchronization and coherency, | *** | *** | |
| 43 | Type of shared Memory multiprocessors, | *** | *** | |
| 44 | Memory Coherence in shared Memory Multiprocessors. | |||
| 12 | 45 | Test | *** | *** |
| 46 | Problem Solving | |||
| 47 | Assignment | *** | *** | |